Latency adjustment method and data stream processing device

ABSTRACT

A latency adjustment method includes the following operations: in response to a predetermined event of a data stream occurred during a first interval, performing a transmission status determining operation to determine whether a transmission status of the data stream is stable; in response the transmission status being stable, determining whether a total number of times of packet loss compensation events of the data stream occurred during a previous interval is higher than a first predetermined value; and in response to the transmission status being unstable or the total number of times being higher than the first predetermined value, increasing a latency of the data stream.

BACKGROUND OF THE INVENTION 1. Field of the Invention

The present disclosure relates to a data stream processing device. Moreparticularly, the present disclosure relates to a data stream processingdevice able to dynamically adjust a latency of a data stream and alatency adjustment method.

2. Description of Related Art

In practical applications, a receiver end cannot receive dataimmediately due to interference. To ensure the smoothness of the finaloutput data stream, the receiver end usually stores data for a period oftime and adds latency to the output data stream. In some relatedapproaches, this latency is set to be a large value to ensure stabletransmission, but such setting is not suitable for applications thatvalue immediacy (e.g., online gaming industry). However, if the latencyis directly set to be a small value, the data stream is easy to stalldue to the influence of interference.

SUMMARY OF THE INVENTION

In some aspects, a latency adjustment method includes the followingoperations: in response to a predetermined event of a data streamoccurred during a first interval, performing a transmission statusdetermining operation to determine whether a transmission status of thedata stream is stable; in response the transmission status being stable,determining whether a total number of times of packet loss compensationevents of the data stream occurred during a previous interval is higherthan a first predetermined value; and in response to the transmissionstatus being unstable or the total number of times being higher than thefirst predetermined value, increasing a latency of the data stream.

In some aspects, a data stream processing device includes a memorycircuit and a processor circuit. The memory circuit is configured tostore at least one program code. The processor circuit is configured toexecute the at least one program code in the memory circuit to: inresponse to a predetermined event of a data stream occurred during afirst interval, perform a transmission status determining operation todetermine whether a transmission status of the data stream is stable; inresponse the transmission status being stable, determine whether a totalnumber of times of packet loss compensation events of the data streamoccurred during a previous interval is higher than a first predeterminedvalue; and in response to the transmission status being unstable or thetotal number of times being higher than the first predetermined value,increase a latency of the data stream.

These and other objectives of the present disclosure will no doubtbecome obvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiments that areillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a schematic diagram of a data stream processing deviceaccording to some embodiments of the present disclosure.

FIG. 1B is a schematic diagram of the processor circuit in FIG. 1Aaccording to some embodiments of the present disclosure.

FIG. 2 is a flow chart of a method for monitoring a transmission statusaccording to some embodiments of the present disclosure.

FIG. 3A and FIG. 3B illustrate a flow chart of a latency adjustmentmethod according to some embodiments of the present disclosure.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The terms used in this specification generally have their ordinarymeanings in the art and in the specific context where each term is used.The use of examples in this specification, including examples of anyterms discussed herein, is illustrative only, and in no way limits thescope and meaning of the disclosure or of any exemplified term.Likewise, the present disclosure is not limited to various embodimentsgiven in this specification.

In this document, the term “coupled” may also be termed as “electricallycoupled,” and the term “connected” may be termed as “electricallyconnected.” “Coupled” and “connected” may mean “directly coupled” and“directly connected” respectively, or “indirectly coupled” and“indirectly connected” respectively. “Coupled” and “connected” may alsobe used to indicate that two or more elements cooperate or interact witheach other. In this document, the term “circuit” may indicate an object,which is formed with one or more transistors and/or one or moreactive/passive elements based on a specific arrangement, for processingsignals.

As used herein, the term “and/or” includes any and all combinations ofone or more of the associated listed items. Although the terms “first,”“second,” etc., may be used herein to describe various elements, theseelements should not be limited by these terms. These terms are used todistinguish one element from another. For example, a first element couldbe termed a second element, and, similarly, a second element could betermed a first element, without departing from the scope of theembodiments. For ease of understanding, like elements in various figuresare designated with the same reference number.

FIG. 1A is a schematic diagram of a data stream processing device 100according to some embodiments of the present disclosure. In someembodiments, the data stream processing device 100 may be, but notlimited to, an audio player device. For example, a data stream SD1 mayinclude multiple sound data, and the data stream processing device 100may be a general headphone, a wireless headphone, or other electronicdevice able to play audio.

In some embodiments, the data stream processing device 100 includes areceiver circuit 110, a buffer circuit 120, a processor circuit 130, anda memory circuit 140. The receiver circuit 110 may receive the datastream SD1 from an external signal source (not shown). The buffercircuit 120 is configured to temporarily store the data stream SD1. Theprocessor circuit 130 may be configured to perform operations in FIG. 2,FIG. 3A, and/or FIG. 3B, in order to adjust a latency of the data streamSD1 temporarily stored in the buffer circuit 120 to generate a datastream SD2.

For example, the data stream SD1 includes data 1-6. The processorcircuit 130 may adjust time difference among the data 1-6 and/or inserta latency TL prior to the data 1-6 according to a current transmissionenvironment, in order to output the data stream SD2. In someembodiments, the latency TL may be located between any two data in thedata 1-6. The location of the latency TL shown is given for illustrativepurposes only, and the present disclosure is not limited thereto. Insome embodiments, the processor circuit 130 may perform a packet losscompensation (PLC) to adjust the latency TL. When a PLC event occurs,the processor circuit 130 stores the current data to the memory circuit140, and the processor circuit 130 may insert the data stored in thememory circuit 140 to the buffer circuit 120 to adjust the latency TL,in order to generate the data stream SD2. Alternatively, in otherexamples, the processor circuit 130 may remove at least one data fromthe data stream SD1 to adjust the latency TL.

In different embodiments, the processor circuit 130 may include, but notlimited to, one or more circuits of a central processing unit (CPU), anapplication-specific integrated circuit, a microcontroller unit, adigital signal processor circuit, and/or a distributed processingsystem. Various circuits or units to implement the processor circuit 130are within the contemplated scope of the present disclosure.

The memory circuit 140 stores at least one program code, which isconfigured to adjust the latency TL. In some embodiments, the processorcircuit 130 may execute the at least one program code stored in thememory circuit 140, in order to perform operations in FIG. 2, FIG. 3A,and/or FIG. 3B. In some embodiments, one or more operations in FIG. 2,FIG. 3A, and/or FIG. 3B may be implemented with software (e.g., programcode, instruction set(s), and so on). In some embodiments, the memorycircuit 140 includes at least one storage circuit which is configured tostore information about a time stamp TS, a predetermined value TH1, apredetermined value TH2, a timer T1, a timer T2, and so on. Theprocessor circuit 130 may utilize such information to perform operationsin FIG. 2, FIG. 3A, and/or FIG. 3B. For example, when a specificcondition is established, the processor circuit 130 may perform certainsoftware or program code(s) to setup the timer T1 in the memory circuit140, in order to start counting (i.e., timing) for a predeterminedinterval (hereinafter referred to as “predetermined interval PT1”).Alternatively, when a specific condition is established, the processorcircuit 130 may delete (e.g., disable or clear) the timer T1 in thememory circuit 140, in order to stop counting for the predeterminedinterval PT1.

In some embodiments, the memory circuit 140 may be a non-transitorycomputer readable storage medium. In some embodiments, the computerreadable storage medium may be, but not limited to, an electronic,magnetic, optical, electromagnetic, infrared, and/or a semiconductordevice. For example, the computer readable storage medium includes asemiconductor or solid-state memory, a magnetic tape, a removablecomputer diskette, a random-access memory (RAM), a read-only memory(ROM), a rigid magnetic disk, and/or an optical disk. In someembodiments, the optical disk may include, but not limited to, CD-ROM,CD-R/W, and/or DVD.

FIG. 1B is a schematic diagram of the processor circuit 130 in FIG. 1Aaccording to some embodiments of the present disclosure. In thisexample, the data stream processing device 100 may be applied to, butnot limited to, a real wireless stereo (RWS) headphone. The processorcircuit 130 includes an interval estimation module 141, a media buffersynchronization module 142, and a PLC module 143. The intervalestimation module 141 may be configured to perform operations in FIG. 2,in order estimate whether a transmission status of the data stream SD1is stable. The media buffer synchronization module 142 is configured toensure that data streams generated from two headphones have the samedata amount. The PLC module 143 is configured to perform the above PLCoperations. The PLC module 143 may duplicate the previous data orperform certain DSP operation(s) according to characteristics of thedata steam SD1 under a condition where the data amount of the datastream SD1 is less, in order to generate sufficient data amount to keepthe data stream SD2.

The modules in FIG. 1B may be implemented with hardware (which mayinclude, but not limited to, integrated circuit(s)), software, or bothof hardware and software. For example in some embodiments, functions ofthe interval estimation module 141 and the media buffer synchronizationmodule 142 may be implemented with certain program codes stored in thememory circuit 140, and the PLC module 143 may be implemented with adigital signal processor (DSP) circuit, but the present disclosure isnot limited thereto.

FIG. 2 is a flow chart of a method 200 for monitoring a transmissionstatus according to some embodiments of the present disclosure. In someembodiments, the processor circuit 130 in FIG. 1 may execute operations(which may be referred to as a “transmission status determiningoperation”) in FIG. 2 to estimate whether the transmission status of thedata stream SD1 is stable.

In operation S205, a standard score of the data stream is compared witha predetermined value TH1. For example, when the receiver circuit 110receives one data in the data stream SD1, the processor circuit 130stores the timestamp TS associated with that data to the memory circuit140. The timestamp TS is to indicate when the data is received. As aresult, the processor circuit 130 may analyze a time difference betweentwo successive data according to the timestamp TS corresponding to eachdata in the data stream SD1, in order to determine the standard score(also known as z-score) of the data stream SD1. The standard score is toevaluate a difference between a time difference between the two mostrecent data in the data stream and the average of all time differencesby using the standard deviation. In other words, if the current standardscore is higher, it indicates that the current transmission status ofthe data stream SD1 is more unstable (compared with the overalltransmission status).

In operation S210, if the standard score is not higher than thepredetermined value TH1, whether a short-term variation of the datastream is lower than a long-term variation the data stream isdetermined. In some embodiments, a number of data covered by theshort-term variation is less than a number of data covered by thelong-term variation. For example, the processor circuit 130 maydetermine time differences among multiple data (which may be, but notlimited to, 16 data) which are recently received by the receiver circuit110 according to the timestamp TS corresponding to those data. As aresult, the processor circuit 130 may utilize the time differences amongthe multiple data to calculate the short-term variation. Similarly, theprocessor circuit 130 may determine time differences among all data thatare currently received by the receiver circuit 110 according to thetimestamp TS corresponding to those data, and utilize those timedifferences to calculate the long-term variation.

In operation S215, if the short-term variation is less than thelong-term variation, a timer for a predetermined interval PT1 is enabled(i.e., start counting for the predetermined interval PT1).Alternatively, if the short-term variation is not less than thelong-term variation, operation S205 is performed again. In operationS220, if the standard score is not higher than the predetermined valueTH1 before the predetermined interval PT1 is expired, the transmissionstatus of the data stream is determined to be stable, and operation S210is performed again. If the short-term variation is less than thelong-term variation, it indicates that the recent transmission status ofthe data stream SD1 is better than the previous overall transmissionstatus of the data stream SD1. Accordingly, the processor circuit 130may setup the timer T1 in the memory circuit 140, in order to startcounting for the predetermined interval PT1. If the processor circuit130 does not detect that the standard score of the data stream SD1 ishigher than the predetermined value TH1 before the predeterminedinterval PT1 is expired, the processor circuit 130 may determine thatthe current transmission status is stable. Alternatively, if theshort-term variation is not lower than the long-term variation, theprocessor circuit 130 may perform operation S205, in order to determinewhether the standard score is higher than the predetermined value TH1again.

In operation S225, if the standard score is higher than thepredetermined value TH1, the transmission status of the data stream isdetermined to be unstable. In operation S230, the standard score is notcompared with the predetermined value TH1 during a predeterminedinterval (hereinafter referred to as “predetermined interval PT2”). Inoperation S235, a timer for an interval (which may be equal to ordifferent from the predetermined interval PT1, and is described as“predetermined interval PT1” in FIG. 2 for illustrative purposes) isdisabled (i.e., stop counting for the predetermined interval PT1), andoperation S205 is performed again.

For example, if the standard score is higher than the predeterminedvalue TH1, it indicates the time difference between the recent two datain the data stream SD1 is too high. Under this condition, the processorcircuit 130 may determine that the transmission status of the datastream SD1 is unstable. In response to the unstable transmission status,the processor circuit 130 may not to compare the standard score with thepredetermined value TH1 (i.e., not to perform operation S205) within thenext predetermined interval PT2 (which may be, but not limited to, 100ms). Under this condition, if the memory circuit 140 stores the timerT1, the processor circuit 130 may delete the timer T1 to stop countingfor the predetermined interval PT1 (or delete a timer different from thetimer T1 to stop counting for the aforementioned interval different fromthe predetermined interval PT1), and perform operation S205 again.

The above description of the method 200 for monitoring the transmissionstatus includes exemplary operations, but the operations of the method200 for monitoring the transmission status are not necessarily performedin the order described above. Operations of the method 200 formonitoring the transmission status can be added, replaced, changedorder, and/or eliminated, or the operations of the method 200 formonitoring the transmission status can be executed simultaneously orpartially simultaneously as appropriate, in accordance with the spiritand scope of various embodiments of the present disclosure.

FIG. 3A and FIG. 3B illustrate a flow chart of a latency adjustmentmethod 300 according to some embodiments of the present disclosure. Insome embodiments, the latency adjustment method 300 may be (but notlimited to) performed by the processor circuit 130 in FIG. 1. Thelatency adjustment method 300 includes operations for increasing thelatency shown in FIG. 3A and operations for decreasing the latency shownin FIG. 3B. In some embodiments, the method 200 for monitoring thetransmission status in FIG. 2 and the latency adjustment method 300shown in FIG. 3A and FIG. 3B may be executed simultaneously or partiallysimultaneously.

Reference is made to FIG. 3A, in operation S310, in response to apredetermined event of the data stream occurred during a first interval,the transmission status determining operation is performed to determinewhether the transmission status of the data stream is stable. In someembodiments, the predetermined event may include, but not limited to, apredetermined number of PLC events, in which the predetermined numbermay be equal to or higher than 1. The predetermined number is set to 2for illustrative purposes in this embodiment. When a first PLC event ofthe data stream SD1 is occurred, the processor circuit 130 may determinewhether the data stream SD1 has another PLC event within the firstinterval (which may be, but not limited to, about 300 ms) after thefirst PLC event the data stream SD1. If the data stream SD1 has a secondPLC event within the first interval, the processor circuit 130 mayutilize operations in FIG. 2 to determine whether the transmissionstatus of the data stream SD1 is stable.

In operation S315, in response to the stable transmission status,whether a total number of times of PLC events of the data streamoccurred during a previous interval is higher than the predeterminedvalue TH2 is determined. If the total number of times of PLC events ofthe data stream SD1 occurred during the previous interval is higher thanthe predetermined value TH2, operation S320 is performed. Alternatively,if the total number of times of PLC events of the data stream SD1occurred during the previous interval is not higher than thepredetermined value TH2, operation S325 is performed. In operation S320,the latency is increased, and a timer for a predetermined interval(hereinafter referred to as “predetermined interval PT3”) is enabled(i.e., start counting for the predetermined interval PT3). In operationS325, the latency is not increased.

For example, whenever the processor circuit 130 performs the PLC to thedata stream SD1, the processor circuit 130 may record information aboutthe number of times for performing the PLC to the memory circuit 140. Ifthe processor circuit 130 determines that the transmissions status ofthe data stream SD1 is stable, processor circuit 130 may determinewhether the total number of times for performing the PLC operationsduring the previous interval is higher than the predetermined value TH2(which may be, but not limited to, 3 or 5). In some embodiments, theprevious interval may be a predetermined interval before the executionof operation S315. In some embodiments, the previous interval may be setby one or more timers. In some embodiments, the previous interval may bean interval between the data stream processing device 100 beginning toreceive the data stream SD1 and the execution of operation S315. If thetotal number of times of PLC events of the data stream SD1 occurredduring the previous interval is higher than the predetermined value TH2,it indicates that the transmission ability of the external signal sourcemay be poor. For example, a predetermined transmission interval ofcertain signal sources may be longer, such that the processor circuit130 determines that the transmission status of the data stream SD1 isstable in operation S310. However, in practical applications, in orderto compensate the longer transmission interval, the processor circuit130 may perform a number of PLC operations to avoid data interruption inthe data stream SD2. In order to identify such external signal sources,in response to the total number of times higher than the predeterminedvalue TH2 (i.e., if the total number of times of PLC events of the datastream SD1 occurred during the previous interval is higher than thepredetermined value TH2), the processor circuit 130 may keep the datautilized in the PLC operation, in order to increase the latency TL.Afterwards, the processor circuit 130 may setup the timer T2 in thememory circuit 140, in order to start counting for the predeterminedinterval PT3 (which may be, but not limited to, 10 seconds).Alternatively, in response to the total number of times not higher thanthe predetermined value TH2, the processor circuit 130 may delete thefollow-up data in the data stream SD1, in order not to increase thelatency TL.

In operation S330, in response to the unstable transmission status, thelatency of the data stream is increased, and the timer for thepredetermined interval PT3 is disabled (i.e., stop counting for thepredetermined interval PT3), in order to perform operation S310 again.For example, if the processor circuit 130 utilizes operations in FIG. 2to determine that the transmission status of the data stream SD1 isunstable, the processor circuit 130 may keep the data utilized in thePLC operations, in order to increase the latency TL. Afterwards, theprocessor circuit 130 checks whether the memory circuit 140 stores thetimer T2. If the memory circuit 140 stores the timer T2, the processorcircuit 130 may delete the timer T2 to stop counting for thepredetermined interval PT3, and perform operation S310 again. As aresult, if the transmission status of the data stream SD1 keeps beingpoor, the processor circuit 130 is able to utilize the above operationsto dynamically increase the latency TL.

In operation S335, if the predetermined event of the data stream is notoccurred during the first interval, whether the total number of times ofPLC events of the data stream occurred during the previous interval ishigher than a value (which may be equal to or different from thepredetermined value TH2, and is described as “predetermined value TH2”in FIG. 3A for illustrative purposes)” is determined. In operation S340,the latency is increased, and the timer for the predetermined intervalPT3 is enabled (i.e., start counting for the predetermined intervalPT3). In operation S345, the latency is not increased. Similar tooperation S315 to operation S325, if the predetermined event of the datastream SD1 is not occurred during the first interval, the processorcircuit 130 may determine whether the total number of times forperforming the PLC operation(s) during the previous interval is higherthan the value that may be equal to or different from the predeterminedvalue TH2. In response to the total number of times higher than thevalue that may be equal to or different from the predetermined valueTH2, the processor circuit 130 may keep the data utilized in the PLCoperation, in order to increase the latency TL. Afterwards, theprocessor circuit 130 may setup the timer T2 in the memory circuit 140,in order to start counting for the predetermined interval PT3.Alternatively, in response to the total number of times not higher thanthe value that may be equal to or different from the predetermined valueTH2, the processor circuit 130 may adjust the follow-up data in the datastream SD1, in order to not to increase the latency TL.

Accordingly, the processor circuit 130 may determine whether to increasethe latency TL according to the transmission status obtained byoperations in FIG. 2 (e.g., operation S310) and the total number timesof PLC events occurred. In other words, the processor circuit 130 isable to adjust the latency TL in real time according to the currentreceiving status of the receiver circuit 110 and/or the transmissionstability of the external signal source.

Reference is made to FIG. 3B, based on different triggering conditions,the processor circuit 130 may perform any of operations shown in FIG.3B, in order to dynamically adjust the latency TL. In operation S350, ifthe predetermined interval PT3 is expired, the latency is decreased, andthe timer for the predetermined interval PT3 is re-enabled (i.e.,restart counting for the predetermined interval PT3). For example, inoperation S320 or S340 in FIG. 3A, the timer T2 is setup. When the timerT2 is expired, if there is no other event (e.g., PLC event or thetransmission status of the data stream SD1 is unstable), the processorcircuit 130 may decrease the latency TL, and re-setup the timer T2, inorder to start counting for the predetermined interval PT3 again. As aresult, if the predetermined interval PT3 is expired and there is noother event, the processor circuit 130 may perform operation S350 againto decrease the latency TL step by step.

In operation S355, if the transmission status of the data stream isstable, the latency is decreased, and the timer for the predeterminedinterval PT3 is re-enabled (i.e., re-start counting for thepredetermined interval PT3). For example, in operation S310 of FIG. 3A,the processor circuit 130 determines that the transmission status of thedata stream SD1 is unstable. In the following operations, if theprocessor circuit 130 determines that the transmission status of thedata stream SD1 becomes stable with operations in FIG. 2, the processorcircuit 130 may decrease the latency TL and re-setup the timer T2, inorder to start counting for the predetermined interval PT3 again. As aresult, if the predetermined interval PT3 is expired and there is noother event, the processor circuit 130 may perform operation S350 againto decrease the latency TL step by step. In some embodiments, before theprocessor circuit 130 decreases the latency TL and re-setups the timerT2, the processor circuit 130 checks whether the current latency TL iswithin an initial range.

In operation S360, if the transmission status of the data stream isunstable, the timer for the predetermined interval PT3 is disabled(i.e., stop counting for the predetermined interval PT3). For example,the processor circuit 130 may determine that the transmission status ofthe data stream SD1 becomes unstable in the course of decreasing thelatency TL. Under this condition, if the processor circuit 130determines that the memory circuit 140 stores the timer T2, theprocessor circuit 130 may delete the timer T2, in order to stop countingfor the predetermined interval PT3. As a result, the processor circuit130 may instantly perform operation S310 in FIG. 3A again, in order todetermine whether to adjust the latency TL.

The above description of the latency adjustment method 300 includesexemplary operations, but the operations of the latency adjustmentmethod 300 are not necessarily performed in the order described above.Operations of the latency adjustment method 300 can be added, replaced,changed order, and/or eliminated, or the operations of the latencyadjustment method 300 can be executed simultaneously or partiallysimultaneously as appropriate, in accordance with the spirit and scopeof various embodiments of the present disclosure.

As described above, the data stream processing device and the latencyadjustment method provided in some embodiments of the present disclosureare able to adjust the latency of the data stream in real time accordingto the transmission status of the current data stream and the number ofPLC events. As a result, the interruption of the data stream is avoided,and the latency can be increased or decreased instantly to improveusers' experience.

Various functional components or blocks have been described herein. Aswill be appreciated by persons skilled in the art, in some embodiments,the functional blocks will preferably be implemented through circuits(either dedicated circuits, or general purpose circuits, which operateunder the control of one or more processors and coded instructions),which will typically comprise transistors or other circuit elements thatare configured in such a way as to control the operation of thecircuitry in accordance with the functions and operations describedherein. As will be further appreciated, the specific structure orinterconnections of the circuit elements will typically be determined bya compiler, such as a register transfer language (RTL) compiler. RTLcompilers operate upon scripts that closely resemble assembly languagecode, to compile the script into a form that is used for the layout orfabrication of the ultimate circuitry. Indeed, RTL is well known for itsrole and use in the facilitation of the design process of electronic anddigital systems.

The aforementioned descriptions represent merely some embodiments of thepresent disclosure, without any intention to limit the scope of thepresent disclosure thereto. Various equivalent changes, alterations, ormodifications based on the claims of present disclosure are allconsequently viewed as being embraced by the scope of the presentdisclosure.

What is claimed is:
 1. A latency adjustment method, comprising: inresponse to a predetermined event of a data stream occurred during afirst interval, performing a transmission status determining operationto determine whether a transmission status of the data stream is stable;in response the transmission status being stable, determining whether atotal number of times of packet loss compensation events of the datastream occurred during a previous interval is higher than a firstpredetermined value; and in response to the transmission status beingunstable or the total number of times being higher than the firstpredetermined value, increasing a latency of the data stream.
 2. Thelatency adjustment method of claim 1, further comprising: if thepredetermined event of the data stream is not occurred during the firstinterval, determining whether the total number of times is higher than avalue that is equal to or different from the first predetermined value.3. The latency adjustment method of claim 1, wherein increasing thelatency of the data stream comprises: in response to the total number oftimes being higher than the first predetermined value or a valuedifferent from the first predetermined value, increasing the latency ofthe data stream and starting counting for a predetermined interval; andin response to the transmission status being unstable, stopping countingfor the predetermined interval.
 4. The latency adjustment method ofclaim 3, further comprising: if the transmission status of the datastream is stable or the predetermined interval is expired, decreasingthe latency and re-starting counting for the predetermined interval; andif the transmission status of the data stream is unstable, stoppingcounting for the predetermined interval.
 5. The latency adjustmentmethod of claim 1, wherein the latency is not increased in response tothe total number of times being not higher than the first predeterminedvalue or a value different from the first predetermined value.
 6. Thelatency adjustment method of claim 1, wherein performing thetransmission status determining operation to determine whether thetransmission status of the data stream is stable comprises: comparing astandard score of the data stream with a second predetermined value; ifthe standard score is not higher than the second predetermined value,determining whether a short-term variation of the data stream is lowerthan a long-term variation of the data stream, wherein a number of datacovered by the short-term variation is less than a number of datacovered by the long-term variation; if the short-term variation is lowerthan the long-term variation, starting counting for a firstpredetermined interval; if the standard score is not higher than thesecond predetermined value before the first predetermined interval isexpired, determining that the transmission status is stable; and if thestandard score is higher than the second predetermined value,determining that the transmission status is unstable.
 7. The latencyadjustment method of claim 6, wherein if the transmission status isunstable, the standard score is not compared with the secondpredetermined value during a second interval, and the latency adjustmentmethod further comprises: stopping counting for an interval that isequal to or different from the first predetermined interval when thesecond interval is expired.
 8. The latency adjustment method of claim 1,wherein the predetermined event comprises a predetermined number ofpacket loss compensation events.
 9. A data stream processing device,comprising: a memory circuit configured to store at least one programcode; and a processor circuit configured to execute the at least oneprogram code in the memory circuit to: in response to a predeterminedevent of a data stream occurred during a first interval, perform atransmission status determining operation to determine whether atransmission status of the data stream is stable; in response thetransmission status being stable, determine whether a total number oftimes of packet loss compensation events of the data stream occurredduring a previous interval is higher than a first predetermined value;and in response to the transmission status being unstable or the totalnumber of times being higher than the first predetermined value,increase a latency of the data stream.
 10. The data stream processingdevice of claim 9, wherein if the predetermined event of the data streamis not occurred during the first interval, the processor circuit isfurther configured to determine whether the total number of times ishigher than a value that is equal to or different from the firstpredetermined value.
 11. The data stream processing device of claim 9,wherein the processor circuit is configured to increase the latency ofthe data stream and start counting for a predetermined interval inresponse to the total number of times being higher than the firstpredetermined value or a value different from the first predeterminedvalue, and stop counting for the predetermined interval in response tothe transmission status being unstable.
 12. The data stream processingdevice of claim 11, wherein if the transmission status of the datastream is stable or the predetermined interval is expired, the processorcircuit is configured to decrease the latency and re-start counting forthe predetermined interval.
 13. The data stream processing device ofclaim 12, wherein if the transmission status of the data stream isunstable, the processor circuit is further configured to stop countingfor the predetermined interval.
 14. The data stream processing device ofclaim 9, wherein the processor circuit is configured to not increase thelatency in response to the total number of times being not higher than avalue that is equal to or different from the first predetermined value.15. The data stream processing device of claim 9, wherein the processorcircuit is configured to: compare a standard score of the data streamwith a second predetermined value; if the standard score is not higherthan the second predetermined value, determine whether a short-termvariation of the data stream is lower than a long-term variation of thedata stream, wherein a number of data covered by the short-termvariation is less than a number of data covered by the long-termvariation; if the short-term variation is lower than the long-termvariation, start counting for a first predetermined interval; if thestandard score is not higher than the second predetermined value beforethe first predetermined interval is expired, determine that thetransmission status is stable; and if the standard score is higher thanthe second predetermined value, determine that the transmission statusis unstable.
 16. The data stream processing device of claim 15, whereinthe processor circuit is further configured to not compare the standardscore with the second predetermined value during a second interval ifthe transmission status is unstable, and stop counting for an intervalthat is the equal to or different from the first predetermined intervalwhen the second interval is expired.
 17. The data stream processingdevice of claim 9, wherein the predetermined event comprises apredetermined number of packet loss compensation events.